Presentation | 2001/5/18 A Memory Architecture for Low Power MPEG-4 Multi-Codec LSI Akihiko Inone, Masayoshi Toujima, Junji Michiyama, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | In this paper, a memory architecture for low power MPEG-4 video codec LSI is described. 20M-bit embedded DRAM is divided into four 4M-bit macros used as a work area and two 2M-bit macros for a frame buffer. Due to the multi-core architecture, bus traffic can be reduced, and adaptive clock gating of DRAM macros is enabled. The LSI consumes 90row when performing MPEG-4 Simple@L1 codec at the 54MHz |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Memory Architecture / Low Power Design / MPEG-4 System |
Paper # | ICD2001-31 |
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Committee | ICD |
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Conference Date | 2001/5/18(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Registration To | Integrated Circuits and Devices (ICD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | A Memory Architecture for Low Power MPEG-4 Multi-Codec LSI |
Sub Title (in English) | |
Keyword(1) | Memory Architecture |
Keyword(2) | Low Power Design |
Keyword(3) | MPEG-4 System |
1st Author's Name | Akihiko Inone |
1st Author's Affiliation | IT System LSI Development Center of Corporate Development Division of Semiconductor Company of Matsushita Electric Industrial Co., Ltd.() |
2nd Author's Name | Masayoshi Toujima |
2nd Author's Affiliation | IT System LSI Development Center of Corporate Development Division of Semiconductor Company of Matsushita Electric Industrial Co., Ltd. |
3rd Author's Name | Junji Michiyama |
3rd Author's Affiliation | IT System LSI Development Center of Corporate Development Division of Semiconductor Company of Matsushita Electric Industrial Co., Ltd. |
Date | 2001/5/18 |
Paper # | ICD2001-31 |
Volume (vol) | vol.101 |
Number (no) | 85 |
Page | pp.pp.- |
#Pages | 7 |
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