| Presentation | 2001/3/2 A Parallelizing Compiler in a Hardware/Software Cosynthesis System for Image/Video Processor with Packed SIMD Type Instruction Sets Nobuhiro NONOGAKI, Nozomu TOGAWA, Masao YANAGISAWA, Tatsuo OHTSUKI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Many current general purpose processors and digital signal processors have extended instructions to enhance their performance of image/video processing applications. The extended functionality comes primarily with the addition of packed SIMD type instructions. These instructions aim at exploiting subword parallelism. The packed SIMD type instruction set includes hundreds of instructions but a small subset of them is enough to implement most image/video processing applications. Thus we can significantly reduce area of a processor within a restriction of execution time if application-specific syntyesis is applied to it. In this paper, we propose a hardware/software cosynthesis system for processors with packed SIMD type instruction set and an algorithm of SIMD parallelization in a register for its compiler. The input of the system is an application description written in C and application data, and the output is hardware descriptions of a synthesized processor core, an application binary code executed on the processor core and software environment. Its compiler generates an object code assuming a processor core with all the available hardware units. It exploits instruction level and subword level parallelism, and attempts to minimize its execution time. The experimental results show the effectiveness of the compiler. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Hardware/software cosynthesis / packed SIMD type instruction set / digital signal processing / compiler / embedded processors |
| Paper # | VLD2000-139,ICD2000-215 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2001/3/2(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Parallelizing Compiler in a Hardware/Software Cosynthesis System for Image/Video Processor with Packed SIMD Type Instruction Sets |
| Sub Title (in English) | |
| Keyword(1) | Hardware/software cosynthesis |
| Keyword(2) | packed SIMD type instruction set |
| Keyword(3) | digital signal processing |
| Keyword(4) | compiler |
| Keyword(5) | embedded processors |
| 1st Author's Name | Nobuhiro NONOGAKI |
| 1st Author's Affiliation | Dept. of Electronics, Information and Communication Engineering, Waseda University() |
| 2nd Author's Name | Nozomu TOGAWA |
| 2nd Author's Affiliation | Advanced Research Institute for Science and Engineering, Waseda University |
| 3rd Author's Name | Masao YANAGISAWA |
| 3rd Author's Affiliation | Dept. of Electronics, Information and Communication Engineering, Waseda University |
| 4th Author's Name | Tatsuo OHTSUKI |
| 4th Author's Affiliation | Dept. of Electronics, Information and Communication Engineering, Waseda University |
| Date | 2001/3/2 |
| Paper # | VLD2000-139,ICD2000-215 |
| Volume (vol) | vol.100 |
| Number (no) | 648 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |