| Presentation | 2000/11/23 A Memory Power Reduction Technique for Core-base System LSIs Tohru ISHIHARA, Kunihiro ASADA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A system level approach for a memory power reduction is proposed in this paper.The basic idea is allocating frequently executed object codes into a small subprogram memory and optimizing supply voltage and threshold voltage of the subprogram memory.Since large scale memory contains a lot of direct paths from power supply to ground, power dissipation caused by subthreshold leakage current is more serious than dynamic power dissipation.Our approach optimizes the size of subprogram memory, supply voltage, and threshold voltage so as to minimize memory power dissipation including static power dissipation caused by leakage current.A heuristic algorithm which determines code allocation, supply voltage, and threshold voltage simultaneously so as to minimize power dissipation of memories is proposed as well.Our experiments with some benchmark programs demonstrate significant energy reductions up to 80% over a program memory which does not apply our approach. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Low power design / Memory / Voltage scaling / System LSI |
| Paper # | VLD2000-85,ICD2000-142,FTS2000-50 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2000/11/23(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Memory Power Reduction Technique for Core-base System LSIs |
| Sub Title (in English) | |
| Keyword(1) | Low power design |
| Keyword(2) | Memory |
| Keyword(3) | Voltage scaling |
| Keyword(4) | System LSI |
| 1st Author's Name | Tohru ISHIHARA |
| 1st Author's Affiliation | VLSI Design and Education Center, the University of Tokyo() |
| 2nd Author's Name | Kunihiro ASADA |
| 2nd Author's Affiliation | VLSI Design and Education Center, the University of Tokyo |
| Date | 2000/11/23 |
| Paper # | VLD2000-85,ICD2000-142,FTS2000-50 |
| Volume (vol) | vol.100 |
| Number (no) | 474 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |