Presentation	2000/10/16 Design of Source Voltage Controlled Oscillator (SVCO) and Phase Lock Loop Using SVCO Tomochika Harada, Tadayoshi Enomoto,
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Abstract(in English)	A high sensitive 43 stage Source Voltage Controlled Oscillator (SVCO) has been designed using 0.13μm CMOS technology. SPICE simulation results show an output frequency range of the VCO was 100MHz～730MHz, and voltage sensitivity was 1.4GHz/V. A PLL circuit that has implemented the SVCO and 0.13μm CMOS technology, has also been designed. At 526MHz oscillation, SPICE simulation results of the PLL show that power dissipation was about 5.8mW, jitter was 16psec (0.84%), and lock time was 2.6μsec.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	SVCO / PLL / body-bias effect / voltage sensitivity
Paper #	DSP2000-112,ICD2000-105,IE2000-57
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Conference Information
Committee	ICD
Conference Date	2000/10/16(1days)
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Paper Information
Registration To	Integrated Circuits and Devices (ICD)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Design of Source Voltage Controlled Oscillator (SVCO) and Phase Lock Loop Using SVCO
Sub Title (in English)
Keyword(1)	SVCO
Keyword(2)	PLL
Keyword(3)	body-bias effect
Keyword(4)	voltage sensitivity
1st Author's Name	Tomochika Harada
1st Author's Affiliation	Department of Information and System Engineering, Faculty of Science and Engineering, Chuo University.()
2nd Author's Name	Tadayoshi Enomoto
2nd Author's Affiliation	Department of Information and System Engineering, Faculty of Science and Engineering, Chuo University.
Date	2000/10/16
Paper #	DSP2000-112,ICD2000-105,IE2000-57
Volume (vol)	vol.100
Number (no)	386
Page	pp.pp.-
#Pages	7
Date of Issue