| Presentation | 2000/10/16 Novel VLIW Code Compaction Method for a 3D Geometry Processor Hiroaki Suzuki, Hiroshi Makino, Yoshio Matsuda, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A VLIW (Very Long Instruction Word) architecture with a new code compaction method has been proposed. For a 3D-geometry processor, we consider two types of 2-issue VLIW architectures, the floating-point execution accelerating VLIW (FP-VLIW) and the date-move enhancing VLIW (MV-VLIW) architectures, as expansions of a single SIMD (Single Instruction, Multiple Data) architecture. TO solve the code bloat problem in common with VLIW architectures, the proposed method enables to compact original codes into the VLIW codes by software tools and decompact the VLIW codes by a simple hardware decompactor composed of an instruction swap circuit on a chip. Speeds and code densities of the two VLIWs with the compaction method are compared to a reference processor with the same instruction set and the same building blocks. The speed of the FP-VLIW is the fastest in all test cases. It is 26%-30% faster than the reference processor. The proposed compaction method keeps the 94% code density of the reference processor. The FP-VLIW architecture with the code compaction achieves 1.2-1.3 times of the speed performance without the significant code-density deterioration. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | VLIW-code compaction / 3D graphics / Geomeroy engine processor / VLIW Processor / ASSP |
| Paper # | DSP2000-111,ICD2000-104,IE2000-56 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2000/10/16(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Novel VLIW Code Compaction Method for a 3D Geometry Processor |
| Sub Title (in English) | |
| Keyword(1) | VLIW-code compaction |
| Keyword(2) | 3D graphics |
| Keyword(3) | Geomeroy engine processor |
| Keyword(4) | VLIW Processor |
| Keyword(5) | ASSP |
| 1st Author's Name | Hiroaki Suzuki |
| 1st Author's Affiliation | System LSI Development Center, Mitsubishi Electric Corporation() |
| 2nd Author's Name | Hiroshi Makino |
| 2nd Author's Affiliation | System LSI Development Center, Mitsubishi Electric Corporation |
| 3rd Author's Name | Yoshio Matsuda |
| 3rd Author's Affiliation | System LSI Development Center, Mitsubishi Electric Corporation |
| Date | 2000/10/16 |
| Paper # | DSP2000-111,ICD2000-104,IE2000-56 |
| Volume (vol) | vol.100 |
| Number (no) | 386 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |