| Presentation | 2000/10/16 Memory Access Estimation of Filter Bank Implementation on Different DSP Architectures Naoki Mizutani, shogo Muramatsu, Hisakazu Kikuchi, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this report, supposing digital signal processors (DSP) of different architectures, the efficient implementation of filter banks is investigated. Especially, focusing on the memory accesses, the number of memory transfers, the power consumptions and the processing accuracies are discussed. DSP employs the Harvard architecture for fast signal processing and has special functional units, such as multiplier-and-accumulator (MAC) units, Barrel shifters and so forth. Even if looking only the MAC units, however, there are some differences in the number of units, the number of accumulators and so forth. In addition, the processing procedure influences the efficiency of memory accesses and the processing accuracy. It is known that the extra memory accesses affects the power consumption, and is very important problem. On the other hand, filter banks are known as an element technique of subband coding and wavelet coding. Thus, their efficient implementation is expected. In this report, firstly the unified representation of analyses and synthesis banks are introduced and then it is divided into two types of procedures. These procedures are investigated with MAC units of different architectures. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Digital signal processor(DSP) / Filter bank / Wavelet / Multiply and accumulate(MAC) |
| Paper # | DSP2000-105,ICD2000-98,IE2000-50 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2000/10/16(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Memory Access Estimation of Filter Bank Implementation on Different DSP Architectures |
| Sub Title (in English) | |
| Keyword(1) | Digital signal processor(DSP) |
| Keyword(2) | Filter bank |
| Keyword(3) | Wavelet |
| Keyword(4) | Multiply and accumulate(MAC) |
| 1st Author's Name | Naoki Mizutani |
| 1st Author's Affiliation | Faculty of Engineering, Niigata University() |
| 2nd Author's Name | shogo Muramatsu |
| 2nd Author's Affiliation | Faculty of Engineering, Niigata University |
| 3rd Author's Name | Hisakazu Kikuchi |
| 3rd Author's Affiliation | Faculty of Engineering, Niigata University |
| Date | 2000/10/16 |
| Paper # | DSP2000-105,ICD2000-98,IE2000-50 |
| Volume (vol) | vol.100 |
| Number (no) | 386 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |