Presentation 2000/9/15
1ms Vision Chip : State of the Art and Future
Masatoshi Ishikawa,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) Conventional image processing has a critical limit in processing speed derived from VIDEO rate. In order to overcome the limit, fully parallel processing architecture without scanning has been proposed. The architecture will be in a new era based on recent semiconductor integration technology. This means we can use practical devices based on it and the research field of image processing will be changed in near future. In this paper, a vision chip with general purpose processing capabilities developed in our laboratory and its applications will be described.
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Keyword(in English) vision chip / high speed image processing / parallel processing / LSI / robot / optical interconnection
Paper # ICD2000-89
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Conference Information
Committee ICD
Conference Date 2000/9/15(1days)
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Paper Information
Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) 1ms Vision Chip : State of the Art and Future
Sub Title (in English)
Keyword(1) vision chip
Keyword(2) high speed image processing
Keyword(3) parallel processing
Keyword(4) LSI
Keyword(5) robot
Keyword(6) optical interconnection
1st Author's Name Masatoshi Ishikawa
1st Author's Affiliation Department of Mathematical Engineering and Information Physics Graduate School of Engineering University of Tokyo()
Date 2000/9/15
Paper # ICD2000-89
Volume (vol) vol.100
Number (no) 310
Page pp.pp.-
#Pages 8
Date of Issue