Presentation 2000/8/17
ED2000-120 / SDM2000-102 / ICD2000-56 A Low Power Media Processor Core performable CIF30fr/s MPEG4/H26x Video Codec
Hideo Ohira, Toshihisa Kamemaru, Hirokazu Suzuki, Kenichi Asano, Masahiko Yoshimoto,
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Abstract(in English) A architectural design of a media processor core optimized for MPEG4/H26x video codec targeting for mobile multimedia terminals[1]is presented. The architecture consists of unique SIMD(Single Instruction Multiple Data)processor, RISC-processor, VLC-processor, intelligent DMA controller. CIF 30frames/s MPEG4 Simple Profile video codec @ 100MHz is performed. Estimated dissipation is as low as 280mW. 300kgates and 16kBytes four port SRAM are contained on 12mm^2 area using 0.18μm process technology. The combination of RISC-processor and SIMD-processor can also operate MPEG4 core profile(shape coding)that requires flexibility and performance.
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Keyword(in English) MPEG4 / H26x / Media Processor Core / Video Compression
Paper # ED2000-120,SDM2000-102,ICD2000-56
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Conference Date 2000/8/17(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) ED2000-120 / SDM2000-102 / ICD2000-56 A Low Power Media Processor Core performable CIF30fr/s MPEG4/H26x Video Codec
Sub Title (in English)
Keyword(1) MPEG4
Keyword(2) H26x
Keyword(3) Media Processor Core
Keyword(4) Video Compression
1st Author's Name Hideo Ohira
1st Author's Affiliation ()
2nd Author's Name Toshihisa Kamemaru
2nd Author's Affiliation
3rd Author's Name Hirokazu Suzuki
3rd Author's Affiliation
4th Author's Name Kenichi Asano
4th Author's Affiliation
5th Author's Name Masahiko Yoshimoto
5th Author's Affiliation
Date 2000/8/17
Paper # ED2000-120,SDM2000-102,ICD2000-56
Volume (vol) vol.100
Number (no) 269
Page pp.pp.-
#Pages 8
Date of Issue