Presentation 2000/8/17
ED2000-116 / SDM2000-98 / ICD2000-52 A 54x54-b Multiplier with a Triple-Vth CMOS/SIMOX Circuit Scheme
Koji Fujii, Takakuni Douseki,
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Abstract(in English) A54x54-b multiplier was designed and fabricated with a triple threshold CMOS/SIMOX circuit scheme. To accelerate its operation, we developed and used a multiplexer that reduces load capacitance in a critical path. To reduce power consumption, we automatically constructed the CMOS logic ciruit with low and medium-Vth MOSFETs using an EDA tool. The multiplier achieved a delay time of 31 ns and a power dissipation of 2.8 mW at 0.5-V operation.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Triple-threshold circuit / CMOS / SIMOX / low voltage / threshold voltage / multiplier
Paper # ED2000-116,SDM2000-98,ICD2000-52
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Committee ICD
Conference Date 2000/8/17(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) ED2000-116 / SDM2000-98 / ICD2000-52 A 54x54-b Multiplier with a Triple-Vth CMOS/SIMOX Circuit Scheme
Sub Title (in English)
Keyword(1) Triple-threshold circuit
Keyword(2) CMOS
Keyword(3) SIMOX
Keyword(4) low voltage
Keyword(5) threshold voltage
Keyword(6) multiplier
1st Author's Name Koji Fujii
1st Author's Affiliation NTT Telecommunications Energy Laboratories()
2nd Author's Name Takakuni Douseki
2nd Author's Affiliation NTT Telecommunications Energy Laboratories
Date 2000/8/17
Paper # ED2000-116,SDM2000-98,ICD2000-52
Volume (vol) vol.100
Number (no) 269
Page pp.pp.-
#Pages 5
Date of Issue