| Presentation | 2000/8/17 ED2000-115 / SDM2000-97 / ICD2000-51 900MHz 18Mb DDR SRAM Yasuhisa Takeyama, Atsushi Kawasumi, Azuma Suzuki, Hiroshi Hatada, Osamu Hirabayashi, Yasushi Kameda, Takahiro Hamano, Nobuaki Otsuka, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Power reduction techniques suitable for high-speed SRAM are proposed. The proposed sense amplifier can reduce operation current and sensing time due to reduction of total capacitance of read data bus. The proposed self-triggered bit-line load scheme can save power, because no control signal is needed. Using these techniques, an 18Mb DDR SRAM was developed. Under the typical 1.8V condition, operation current is reduced and a 900MHz I/O frequency is achieved. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | SRAM / double data rate / I/O frequency / power reduction |
| Paper # | ED2000-115,SDM2000-97,ICD2000-51 |
| Date of Issue |
| Conference Information | |
| Committee | ICD |
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| Conference Date | 2000/8/17(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | ED2000-115 / SDM2000-97 / ICD2000-51 900MHz 18Mb DDR SRAM |
| Sub Title (in English) | |
| Keyword(1) | SRAM |
| Keyword(2) | double data rate |
| Keyword(3) | I/O frequency |
| Keyword(4) | power reduction |
| 1st Author's Name | Yasuhisa Takeyama |
| 1st Author's Affiliation | Memory LSI Research & Development Center, Toshiba Corporation() |
| 2nd Author's Name | Atsushi Kawasumi |
| 2nd Author's Affiliation | Memory LSI Research & Development Center, Toshiba Corporation |
| 3rd Author's Name | Azuma Suzuki |
| 3rd Author's Affiliation | Memory LSI Research & Development Center, Toshiba Corporation |
| 4th Author's Name | Hiroshi Hatada |
| 4th Author's Affiliation | Memory LSI Research & Development Center, Toshiba Corporation |
| 5th Author's Name | Osamu Hirabayashi |
| 5th Author's Affiliation | Memory LSI Research & Development Center, Toshiba Corporation |
| 6th Author's Name | Yasushi Kameda |
| 6th Author's Affiliation | Memory LSI Research & Development Center, Toshiba Corporation |
| 7th Author's Name | Takahiro Hamano |
| 7th Author's Affiliation | Toshiba Microelectronics Corporation |
| 8th Author's Name | Nobuaki Otsuka |
| 8th Author's Affiliation | Memory LSI Research & Development Center, Toshiba Corporation |
| Date | 2000/8/17 |
| Paper # | ED2000-115,SDM2000-97,ICD2000-51 |
| Volume (vol) | vol.100 |
| Number (no) | 269 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |