Presentation 2000/8/17
ED2000-114 / SDM2000-96 / ICD2000-50 On-Chip Multi-GHz Clocking with Transmission Lines
K Anjo, M Mizuno, Y Sumi, M Fukaishi, H Wakabayashi, T Mogami, T Horiuchi, M Yamashina,
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Abstract(in English) In this paper, clock distribution scheme with on-chip transmission lines is presented. This technique allows clock signals to be transmitted in electro-magnetic speed. This results in smaller clock skew because wire delay deviation caused by device fluctuation can be ignored. The 10×10mm^2 test chip is designed using this technique in 0.1um CMOS technology. The simulated result shows that 5-GHz clock can be distributed with less than 20-ps clock skew.
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Keyword(in English) Microprocessor / clock distribution / transmission line
Paper # ED2000-114,SDM2000-96,ICD2000-50
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Conference Date 2000/8/17(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) ED2000-114 / SDM2000-96 / ICD2000-50 On-Chip Multi-GHz Clocking with Transmission Lines
Sub Title (in English)
Keyword(1) Microprocessor
Keyword(2) clock distribution
Keyword(3) transmission line
1st Author's Name K Anjo
1st Author's Affiliation Silicon Systems Research Laboratories()
2nd Author's Name M Mizuno
2nd Author's Affiliation Silicon Systems Research Laboratories
3rd Author's Name Y Sumi
3rd Author's Affiliation NEC infomatec Systems, Ltd.
4th Author's Name M Fukaishi
4th Author's Affiliation Silicon Systems Research Laboratories
5th Author's Name H Wakabayashi
5th Author's Affiliation Silicon Systems Research Laboratories
6th Author's Name T Mogami
6th Author's Affiliation Silicon Systems Research Laboratories
7th Author's Name T Horiuchi
7th Author's Affiliation ULSI device development department
8th Author's Name M Yamashina
8th Author's Affiliation Silicon Systems Research Laboratories
Date 2000/8/17
Paper # ED2000-114,SDM2000-96,ICD2000-50
Volume (vol) vol.100
Number (no) 269
Page pp.pp.-
#Pages 8
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