| Presentation | 2000/8/17 ED2000-113 / SDM2000-95 / ICD2000-49 Level Converters with High Immunity to Power-Supply Bouncing for High-Speed Sub-1-V LSIs Yusuke Kanno, Hiroyuki Mizuno, Kazuo Tanaka, Takao Watanabe, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We have developed a pump-hopping level-up converter and a differential-input level-down converter that enable level conversion for I/O interfacing sub-1-V LSIs. The level-up converter transforms signals of 0.64 V to 3.6 V within 5 ns with a 0.14-μm CMOS technology. The differential input level down converter enables stable operation even at VDD of 0.5 V. These proposed level converters also provide the immunity against power-supply bouncing, which is essential for low-voltage and high-speed LSIs. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | level converter / I/O circuitry / low voltage / power-supply bouncing / noise immunity |
| Paper # | ED2000-113,SDM2000-95,ICD2000-49 |
| Date of Issue |
| Conference Information | |
| Committee | ICD |
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| Conference Date | 2000/8/17(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | ED2000-113 / SDM2000-95 / ICD2000-49 Level Converters with High Immunity to Power-Supply Bouncing for High-Speed Sub-1-V LSIs |
| Sub Title (in English) | |
| Keyword(1) | level converter |
| Keyword(2) | I/O circuitry |
| Keyword(3) | low voltage |
| Keyword(4) | power-supply bouncing |
| Keyword(5) | noise immunity |
| 1st Author's Name | Yusuke Kanno |
| 1st Author's Affiliation | Central Research Laboratory, Hitachi, Ltd.,() |
| 2nd Author's Name | Hiroyuki Mizuno |
| 2nd Author's Affiliation | Central Research Laboratory, Hitachi, Ltd., |
| 3rd Author's Name | Kazuo Tanaka |
| 3rd Author's Affiliation | Semiconductor & Integrated Circuits Hitachi, Ltd., |
| 4th Author's Name | Takao Watanabe |
| 4th Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. |
| Date | 2000/8/17 |
| Paper # | ED2000-113,SDM2000-95,ICD2000-49 |
| Volume (vol) | vol.100 |
| Number (no) | 269 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |