| Presentation | 2000/8/17 ED2000-112 / SDM2000-94 / ICD2000-48 Skew and Jitter Suppressed DLL Architecture for Over 400 Mbps DDR SDRAMs Takeshi Hamamoto, Satoshi Kawasaki, Kiyohiro Furutani, Kenichi Yasuda, Yasuhiro> Konishi, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper demonstrates a skew and a jitter suppressed delay locked loop(DLL)architecture used for high frequency DDR SDRAMs. Two novel replica adjusting techniques are introduced;1)a direct phase comparing architecture reduces a timing skew caused by clock input circuits, and 2)a wafer level replica adjusting technique enables a precise replica tuning at wafer test. Further, an improved delay line architecture is introduced;3)a novel delay line scheme improves its frequency chariacterstics, and 4)a fine delay regulating scheme suppresses a jitter caused by a hierarcy delay line architecture. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | DDR-SDRAM / DLL / Skew / Jitter / Delay Line / Duty / Replica / Wafer Test |
| Paper # | ED2000-112,SDM2000-94,ICD2000-48 |
| Date of Issue |
| Conference Information | |
| Committee | ICD |
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| Conference Date | 2000/8/17(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | ED2000-112 / SDM2000-94 / ICD2000-48 Skew and Jitter Suppressed DLL Architecture for Over 400 Mbps DDR SDRAMs |
| Sub Title (in English) | |
| Keyword(1) | DDR-SDRAM |
| Keyword(2) | DLL |
| Keyword(3) | Skew |
| Keyword(4) | Jitter |
| Keyword(5) | Delay Line |
| Keyword(6) | Duty |
| Keyword(7) | Replica |
| Keyword(8) | Wafer Test |
| 1st Author's Name | Takeshi Hamamoto |
| 1st Author's Affiliation | ULSI Development Center, Mitsubishi Electric Corp.() |
| 2nd Author's Name | Satoshi Kawasaki |
| 2nd Author's Affiliation | ULSI Development Center, Mitsubishi Electric Corp. |
| 3rd Author's Name | Kiyohiro Furutani |
| 3rd Author's Affiliation | ULSI Development Center, Mitsubishi Electric Corp. |
| 4th Author's Name | Kenichi Yasuda |
| 4th Author's Affiliation | ULSI Development Center, Mitsubishi Electric Corp. |
| 5th Author's Name | Yasuhiro> Konishi |
| 5th Author's Affiliation | ULSI Development Center, Mitsubishi Electric Corp. |
| Date | 2000/8/17 |
| Paper # | ED2000-112,SDM2000-94,ICD2000-48 |
| Volume (vol) | vol.100 |
| Number (no) | 269 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |