| Presentation | 2000/5/4 An accurate RLC interconnection delay calculation for generating RC delay equivalent circuit enclosing inductance effects Patrick Lenoir, Kazuyuki Nakamura, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | With increasing VLSI on-chip frequencies, the importance of interconnection wiring inductance effects, makes no longer trustable the RC models implemented in most of the current CAD-tools. In this paper we focus on accurate estimations of the RLC propagation delay for one wire. Then we generate RC delay equivalent circuits enclosing the inductance effects in order to take advantage of the present CAD-tools. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Inductance / Wiring delay / Delay Modelimg / CAD tool |
| Paper # | ICD2000-18 |
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| Committee | ICD |
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| Conference Date | 2000/5/4(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An accurate RLC interconnection delay calculation for generating RC delay equivalent circuit enclosing inductance effects |
| Sub Title (in English) | |
| Keyword(1) | Inductance |
| Keyword(2) | Wiring delay |
| Keyword(3) | Delay Modelimg |
| Keyword(4) | CAD tool |
| 1st Author's Name | Patrick Lenoir |
| 1st Author's Affiliation | Silicon Systems Research Laboratories NEC Corporation() |
| 2nd Author's Name | Kazuyuki Nakamura |
| 2nd Author's Affiliation | Silicon Systems Research Laboratories NEC Corporation |
| Date | 2000/5/4 |
| Paper # | ICD2000-18 |
| Volume (vol) | vol.100 |
| Number (no) | 41 |
| Page | pp.pp.- |
| #Pages | 7 |
| Date of Issue | |