Presentation 2000/5/4
A High-Speed Low-Power Pixel-Parallel Fingerprint Identification Circuit Scheme
Satoshi SHIGEMATSU, Hiroki MORIMURA,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) Nowadays, user authentication is strongly required to prevent user's mobile equipment from illegal use. This report presents a new fingerprint identification circuit scheme for a single-chip fingerprint sensor and identifier. In this scheme, the identifying circuit is composed of a pixel array, and this circuit can correct the deviation of the sensed image's location and compare the images by using the parallel processing of these pixels. Applying this circuit to a single-chip fingerprint sensor and identifier confirms 100-ms 6.2mW fingerprint identification. This scheme realizes the fingerprint identification system on a single chip.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) fingerprint sensor / Fingerprint identification / pixel parallel / pixel array
Paper # ICD2000-16
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Conference Information
Committee ICD
Conference Date 2000/5/4(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A High-Speed Low-Power Pixel-Parallel Fingerprint Identification Circuit Scheme
Sub Title (in English)
Keyword(1) fingerprint sensor
Keyword(2) Fingerprint identification
Keyword(3) pixel parallel
Keyword(4) pixel array
1st Author's Name Satoshi SHIGEMATSU
1st Author's Affiliation NTT Lifestyle and Environmental Technology Laboratories()
2nd Author's Name Hiroki MORIMURA
2nd Author's Affiliation NTT Lifestyle and Environmental Technology Laboratories
Date 2000/5/4
Paper # ICD2000-16
Volume (vol) vol.100
Number (no) 41
Page pp.pp.-
#Pages 6
Date of Issue