| Presentation | 2000/5/5 A Dynamically Controllable DC/DC Level Converter and Its Application to High-Speed, Low-Power Circuits H. Shikano, H. Ishiyama, H. Iwata, T. Enomoto, M. Fujii, N. Yoshida, |
|---|---|
| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A new DC / DC level converter has been developed for use in high-speed, low-power circuits. The level converter can increase the DC voltage which is supplied to an active-load circuit on request, or supply a minimal DC voltage to a load circuit in the stand-by mode. 32-word register files and 512-bit cache SRAMs were developed using 0.25-μm HEMT technology to examine the effectiveness of the DC / DC level converter in power reduction. Experimental results showed that the power dissipation P of the 32-word register file with on-chip DC / DC level converters was 1.04W, a reduction to 57.1% of that of an equivalent conventional register file, while the operating frequency f_C was 6.42 GHz that is 92.9% of f_C for the conventional register file. P for the 512-bit cache SRAM with the new DC / DC level converters was 34.3mW, 89.7% of the value for an equivalent conventional cache SRAM. The DC / DC level converter technology is also useful in that is reduces P due to subthreshold currents in CMOS and pass-transistor logic circuits. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | DC / DC level converter / SRAM / register file / delay flip-flop / power dissipation / HEMT |
| Paper # | ICD2000-23 |
| Date of Issue |
| Conference Information | |
| Committee | ICD |
|---|---|
| Conference Date | 2000/5/5(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Dynamically Controllable DC/DC Level Converter and Its Application to High-Speed, Low-Power Circuits |
| Sub Title (in English) | |
| Keyword(1) | DC |
| Keyword(2) | DC level converter |
| Keyword(3) | SRAM |
| Keyword(4) | register file |
| Keyword(5) | delay flip-flop |
| Keyword(6) | power dissipation |
| Keyword(7) | HEMT |
| 1st Author's Name | H. Shikano |
| 1st Author's Affiliation | Graduate School of Science and Engineering, Chuo University() |
| 2nd Author's Name | H. Ishiyama |
| 2nd Author's Affiliation | Graduate School of Science and Engineering, Chuo University |
| 3rd Author's Name | H. Iwata |
| 3rd Author's Affiliation | / Graduate School of Science and Engineering, Chuo University |
| 4th Author's Name | T. Enomoto |
| 4th Author's Affiliation | Optoelectronics and High Frequency Device Res.Labs., NEC Corp. |
| 5th Author's Name | M. Fujii |
| 5th Author's Affiliation | Optoelectronics and High Frequency Device Res.Labs., NEC Corp. |
| 6th Author's Name | N. Yoshida |
| 6th Author's Affiliation | |
| Date | 2000/5/5 |
| Paper # | ICD2000-23 |
| Volume (vol) | vol.100 |
| Number (no) | 42 |
| Page | pp.pp.- |
| #Pages | 7 |
| Date of Issue | |