Presentation | 2000/4/14 A Channel Erasing 1.8V-Only 32Mb NOR Flash EEPROM with a Bit Line Direct Sensing Scheme Y Takano, A Umezawa, T Tanzawa, T Taura, H Shiga, T Miyaba, M Matsui, K Watanabe, K Isobe, S Kitamura, S Yamada, M Saito, S Mori, T Watanabe, S Atsumi, |
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PDF Download Page | PDF download Page Link |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | A 1.8V only 32Mb NOR flash EEPROM has been developed. A channel erasing scheme has been implemented to realize smallest cell size of 0.49μm^2 for 0.25μm CMOS technology. A block decorder circuit with a novel erase-reset sequence has been designed for the channel-erasing operation. A fast access time of 90ns@1.8V has been successfully obtained by a bit line direct sensing scheme, a word line boosted voltage pooling method. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | flash EEPROM / channel erasing / sense amplifier / word line boosted |
Paper # | ICD2000-13 |
Date of Issue |
Conference Information | |
Committee | ICD |
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Conference Date | 2000/4/14(1days) |
Place (in Japanese) | (See Japanese page) |
Place (in English) | |
Topics (in Japanese) | (See Japanese page) |
Topics (in English) | |
Chair | |
Vice Chair | |
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Paper Information | |
Registration To | Integrated Circuits and Devices (ICD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | A Channel Erasing 1.8V-Only 32Mb NOR Flash EEPROM with a Bit Line Direct Sensing Scheme |
Sub Title (in English) | |
Keyword(1) | flash EEPROM |
Keyword(2) | channel erasing |
Keyword(3) | sense amplifier |
Keyword(4) | word line boosted |
1st Author's Name | Y Takano |
1st Author's Affiliation | Microelectronics Engineering Laboratory, Toshiba Semiconductor Company, Toshiba Corporation() |
2nd Author's Name | A Umezawa |
2nd Author's Affiliation | Microelectronics Engineering Laboratory, Toshiba Semiconductor Company, Toshiba Corporation |
3rd Author's Name | T Tanzawa |
3rd Author's Affiliation | Microelectronics Engineering Laboratory, Toshiba Semiconductor Company, Toshiba Corporation |
4th Author's Name | T Taura |
4th Author's Affiliation | Memory Division, Toshiba Semiconductor Company, Toshiba Corporation |
5th Author's Name | H Shiga |
5th Author's Affiliation | Microelectronics Engineering Laboratory, Toshiba Semiconductor Company, Toshiba Corporation |
6th Author's Name | T Miyaba |
6th Author's Affiliation | Advanced LSI Technology Development Department, Toshiba Microelectronics Corporation |
7th Author's Name | M Matsui |
7th Author's Affiliation | Microelectronics Engineering Laboratory, Toshiba Semiconductor Company, Toshiba Corporation |
8th Author's Name | K Watanabe |
8th Author's Affiliation | Microelectronics Engineering Laboratory, Toshiba Semiconductor Company, Toshiba Corporation |
9th Author's Name | K Isobe |
9th Author's Affiliation | System LSI Division, Toshiba Semiconductor Company, Toshiba Corporation |
10th Author's Name | S Kitamura |
10th Author's Affiliation | Microelectronics Engineering Laboratory, Toshiba Semiconductor Company, Toshiba Corporation |
11th Author's Name | S Yamada |
11th Author's Affiliation | Microelectronics Engineering Laboratory, Toshiba Semiconductor Company, Toshiba Corporation |
12th Author's Name | M Saito |
12th Author's Affiliation | Microelectronics Engineering Laboratory, Toshiba Semiconductor Company, Toshiba Corporation |
13th Author's Name | S Mori |
13th Author's Affiliation | Microelectronics Engineering Laboratory, Toshiba Semiconductor Company, Toshiba Corporation |
14th Author's Name | T Watanabe |
14th Author's Affiliation | Microelectronics Engineering Laboratory, Toshiba Semiconductor Company, Toshiba Corporation |
15th Author's Name | S Atsumi |
15th Author's Affiliation | Microelectronics Engineering Laboratory, Toshiba Semiconductor Company, Toshiba Corporation |
Date | 2000/4/14 |
Paper # | ICD2000-13 |
Volume (vol) | vol.100 |
Number (no) | 6 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |