Presentation 2000/4/14
Current Status of PPRAM(Parallel Processing RAM)
Kazuaki Murakami,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) The paper outlines the current status of PPRAM-related projects at Kyushu University and other institutes: (1)PPRAM-Link specifications; (2)PPRAM-Link interface IP cores; (3)DRAM refresh architectures; (4)cache-memory architectures for PPRAM-type SOCs, such as variable line-size cache and way-predicting set-associative cache; (5)reference PPRAM architecture; (6)PPRAM applications such as PPRAM-MOE.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) MDL(merged DRAM/logic) / EML(embedded-memory logic) / system LSI / SOC(system-on-chip) / memory / processor / architecture / PPRAM(parallel processing RAM)
Paper # ICD2000-11
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Conference Date 2000/4/14(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Current Status of PPRAM(Parallel Processing RAM)
Sub Title (in English)
Keyword(1) MDL(merged DRAM/logic)
Keyword(2) EML(embedded-memory logic)
Keyword(3) system LSI
Keyword(4) SOC(system-on-chip)
Keyword(5) memory
Keyword(6) processor
Keyword(7) architecture
Keyword(8) PPRAM(parallel processing RAM)
1st Author's Name Kazuaki Murakami
1st Author's Affiliation Department of Computer Science and Communication Engineering Kyushu University()
Date 2000/4/14
Paper # ICD2000-11
Volume (vol) vol.100
Number (no) 6
Page pp.pp.-
#Pages 6
Date of Issue