| Presentation | 2000/4/14 A DRAM SYSTEM FOR CONSISTENTLY REDUCING CPU WAIT CYCLES Yusuke Kanno, Hiroyuki Mizuno, Takao Watanabe, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A DRAM system is proposed for consistently reducing CPU wait cycles in a cache-based memory hierarchy. This system exhibits a fast write back operation by using an arithmetic address mapping scheme and pseudo dual-port DRAM. The address-mapping scheme generates DRAM bank address by adding'index'and'Tag'fields of address. This enables bank-conflict-free access both in the spatially localized access ('Index'field changes )and the wtite-back access ('Tag'field changes), that are dominant for DRAM main memory access.The pseudo dual-port DRAM scheme enables simultaneous operation of a read and a write accesses associated with'write back'accesses without having extra I/O port. The propsed schemes reduce the expectation value of CPU wait cycles by 38% for sequential accesses and by 43% for an access followed write-back access. As a result, the total access time of carrying out benchmark programs are reduced by 14.3% in average. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | CPU / cache / DRAM / spatially localized access / write-back access / address mapping |
| Paper # | ICD2000-10 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2000/4/14(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A DRAM SYSTEM FOR CONSISTENTLY REDUCING CPU WAIT CYCLES |
| Sub Title (in English) | |
| Keyword(1) | CPU |
| Keyword(2) | cache |
| Keyword(3) | DRAM |
| Keyword(4) | spatially localized access |
| Keyword(5) | write-back access |
| Keyword(6) | address mapping |
| 1st Author's Name | Yusuke Kanno |
| 1st Author's Affiliation | Central Research Laboratory, Hitachi, Ltd., Kokubunji, Tokyo, Japan() |
| 2nd Author's Name | Hiroyuki Mizuno |
| 2nd Author's Affiliation | Central Research Laboratory, Hitachi, Ltd., Kokubunji, Tokyo, Japan |
| 3rd Author's Name | Takao Watanabe |
| 3rd Author's Affiliation | Central Research Laboratory, Hitachi, Ltd., Kokubunji, Tokyo, Japan |
| Date | 2000/4/14 |
| Paper # | ICD2000-10 |
| Volume (vol) | vol.100 |
| Number (no) | 6 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |