Presentation | 2000/4/14 New Architecture for Cost-Efficient High-Performance Multiple-Bank RDRAM Seiro Imai, Takeshi Nagai, Satoru Takase, Hideo Mukai, Hiroshi Maejima, Mikihiko Ito, Hiroko Waki, Kiyofumi Sakurai, Takahiko Hara, Masaru Koyanagi, Kaoru Nakagawa, |
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PDF Download Page | PDF download Page Link |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | A 288Mb RDRAM has been developed using 0.175um CMOS technology to achieve an interleave operation of 2x16 split dependent banks with 2GB/s data rate. It features dual page size of 1KB and 2KB for widespread use, memory core arrangement which suits creation of a cut-down device for high productivity, and shared data transmission system among all banks to improve area efficiency. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | RDRAM / multiple bank / page size / memory core / cost-efficiency |
Paper # | ICD2000-9 |
Date of Issue |
Conference Information | |
Committee | ICD |
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Conference Date | 2000/4/14(1days) |
Place (in Japanese) | (See Japanese page) |
Place (in English) | |
Topics (in Japanese) | (See Japanese page) |
Topics (in English) | |
Chair | |
Vice Chair | |
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Assistant |
Paper Information | |
Registration To | Integrated Circuits and Devices (ICD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | New Architecture for Cost-Efficient High-Performance Multiple-Bank RDRAM |
Sub Title (in English) | |
Keyword(1) | RDRAM |
Keyword(2) | multiple bank |
Keyword(3) | page size |
Keyword(4) | memory core |
Keyword(5) | cost-efficiency |
1st Author's Name | Seiro Imai |
1st Author's Affiliation | Micro electronics Engineering Laboratory, Toshiba Corporation() |
2nd Author's Name | Takeshi Nagai |
2nd Author's Affiliation | Micro electronics Engineering Laboratory, Toshiba Corporation |
3rd Author's Name | Satoru Takase |
3rd Author's Affiliation | Micro electronics Engineering Laboratory, Toshiba Corporation |
4th Author's Name | Hideo Mukai |
4th Author's Affiliation | Micro electronics Engineering Laboratory, Toshiba Corporation |
5th Author's Name | Hiroshi Maejima |
5th Author's Affiliation | Micro electronics Engineering Laboratory, Toshiba Corporation |
6th Author's Name | Mikihiko Ito |
6th Author's Affiliation | Micro electronics Engineering Laboratory, Toshiba Corporation |
7th Author's Name | Hiroko Waki |
7th Author's Affiliation | Toshiba Microelectronics Corporation |
8th Author's Name | Kiyofumi Sakurai |
8th Author's Affiliation | Toshiba Microelectronics Corporation |
9th Author's Name | Takahiko Hara |
9th Author's Affiliation | Micro electronics Engineering Laboratory, Toshiba Corporation |
10th Author's Name | Masaru Koyanagi |
10th Author's Affiliation | DRAM Product Design Department, Toshiba Corporation |
11th Author's Name | Kaoru Nakagawa |
11th Author's Affiliation | Micro electronics Engineering Laboratory, Toshiba Corporation |
Date | 2000/4/14 |
Paper # | ICD2000-9 |
Volume (vol) | vol.100 |
Number (no) | 6 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |