| Presentation | 2000/3/3 Simultaneous Searching Method of Placement and Global Routing with Sequence-Pair and Flip Norimitsu SAKAI, Kouji KIYOTA, Kunihiro FUJIYOSHI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In VLSI layout design, placement and routing are done independently. But it is desired that these are done simultaneously, since the evaluation of the placement may be different from the evaluation of the final layout. Recently, a method to place and route simultaneously, by using BSG (representation of placement) and Flip (routing technique) was proposed. However, unused region and bends of wires may increase by the property of BSG. In this paper, a new method to place and route simultaneously by using floorplan made of sequence-pair, instead of BSG, with Flip is proposed. The experimental results show the effectiveness of the proposed method. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | sequence-pair / floorplan / Flip / place-and-route optimization / Simulated Annealing |
| Paper # | VLD99-120,ICD99-277 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2000/3/3(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Simultaneous Searching Method of Placement and Global Routing with Sequence-Pair and Flip |
| Sub Title (in English) | |
| Keyword(1) | sequence-pair |
| Keyword(2) | floorplan |
| Keyword(3) | Flip |
| Keyword(4) | place-and-route optimization |
| Keyword(5) | Simulated Annealing |
| 1st Author's Name | Norimitsu SAKAI |
| 1st Author's Affiliation | Department of Electrical and Electronic Engineering, Tokyo University of Agriculture & Technology() |
| 2nd Author's Name | Kouji KIYOTA |
| 2nd Author's Affiliation | Department of Electrical and Electronic Engineering, Tokyo University of Agriculture & Technology |
| 3rd Author's Name | Kunihiro FUJIYOSHI |
| 3rd Author's Affiliation | Department of Electrical and Electronic Engineering, Tokyo University of Agriculture & Technology |
| Date | 2000/3/3 |
| Paper # | VLD99-120,ICD99-277 |
| Volume (vol) | vol.99 |
| Number (no) | 661 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |