| Presentation | 2000/1/21 Variable Threshold Filed-Effect-Transistor with Paired Gates Fabricated by Using the Wafer-Bonding Techniqe Satoshi KODAMA, Tomofumi FURUTA, Hiroshi ITO, Noriyuki WATANABE, Atsushi KANDA, Masahiro MURAGUCHI, Tadao ISHIBASHI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We investigated a novel heterostructure field-effect transistor (HFET) with paired gates (PGs), where one gate is above and the other below the channel. Using the wafer-bonding technique, we succeeded in fabricating AlGaAs/InGaAs PG-HFETs on a 3-inch-diameter wafer. The static characteristics of the fabricated HFET indicate that the drain current (I_D) is controlled by the paired gates, providing maximum transconductance of 240 mS/mm. Since the drain current can be controlled by each gate voltage independently, the PG-HFET accepts two gate input signals and functions as a variable threshold HFET. PG-FETs have the unique feature of variable threshold voltage, higher transconductance, lower drain-source capacitance and better subthreshold characteristics. Thus, they will be valuable in creating a new class of microwave and digital circuits. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | wafer-bonding / variable threshold voltage / two-gate-input / HFET / InGaAs |
| Paper # | ED99-279,MW99-203,ICD99-254 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2000/1/21(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Variable Threshold Filed-Effect-Transistor with Paired Gates Fabricated by Using the Wafer-Bonding Techniqe |
| Sub Title (in English) | |
| Keyword(1) | wafer-bonding |
| Keyword(2) | variable threshold voltage |
| Keyword(3) | two-gate-input |
| Keyword(4) | HFET |
| Keyword(5) | InGaAs |
| 1st Author's Name | Satoshi KODAMA |
| 1st Author's Affiliation | NTT Phtonics Labs.() |
| 2nd Author's Name | Tomofumi FURUTA |
| 2nd Author's Affiliation | NTT Phtonics Labs. |
| 3rd Author's Name | Hiroshi ITO |
| 3rd Author's Affiliation | NTT Phtonics Labs. |
| 4th Author's Name | Noriyuki WATANABE |
| 4th Author's Affiliation | NTT Phtonics Labs. |
| 5th Author's Name | Atsushi KANDA |
| 5th Author's Affiliation | NTT Phtonics Labs. |
| 6th Author's Name | Masahiro MURAGUCHI |
| 6th Author's Affiliation | NTT Electronics Corporation |
| 7th Author's Name | Tadao ISHIBASHI |
| 7th Author's Affiliation | NTT Phtonics Labs. |
| Date | 2000/1/21 |
| Paper # | ED99-279,MW99-203,ICD99-254 |
| Volume (vol) | vol.99 |
| Number (no) | 561 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |