| Presentation | 1999/9/21 A feasibility study of 2GHz CMOS PLL frequency synthesizer : Development of RF circuit design technology with CAD Satoshi Sugino, Yasuko Yamamoto, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | RF-IC / Phase Locked Loop / Frequency Synthesizer / CMOS-IC / Phase Noise |
| Paper # | ICD99-171 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 1999/9/21(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A feasibility study of 2GHz CMOS PLL frequency synthesizer : Development of RF circuit design technology with CAD |
| Sub Title (in English) | |
| Keyword(1) | RF-IC |
| Keyword(2) | Phase Locked Loop |
| Keyword(3) | Frequency Synthesizer |
| Keyword(4) | CMOS-IC |
| Keyword(5) | Phase Noise |
| 1st Author's Name | Satoshi Sugino |
| 1st Author's Affiliation | Semicionductor Technology Research Center Matsushita Electric Works,Ltd.() |
| 2nd Author's Name | Yasuko Yamamoto |
| 2nd Author's Affiliation | Semicionductor Technology Research Center Matsushita Electric Works,Ltd. |
| Date | 1999/9/21 |
| Paper # | ICD99-171 |
| Volume (vol) | vol.99 |
| Number (no) | 316 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |