| Presentation | 1999/7/23 Bottom Electrode Structures of Pt/Ru Deposited on Polycrystalline Silicon for Semiconductor Memory Capacitors Eun-Suck Choi, Jun-Sik Hwang, Jong-Bong Park, Soon-Gil Yoon, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The ruthenium buffer layers for platinum deposition onto polycrystalline silicon (poly-Si) were formed by dc sputtering and metalorganic chemical vapor deposition (MOCVD) for high dielectric constant (Ba,Sr)TiO_3 (BST) capacitor integration. The electrode structures of Pt/dc-sputtered Ru/poly-Si annealed for 1h at 700℃ in oxygen ambient (760 Torr) showed severe intermixing between Pt and Ru and showed greatly rough morphologies by the RuO_x phases formed on platinum surface during annealing in O_2. On the other hand, those of Pt/MOCVD-Ru/poly-Si annealed at 700℃ showed smooth surface microstructure without any second phases on platinum. Contacts in the annealed Pi/dc-sputtered Ru/poly-Si and Pt/MOCVD-Ru/poly-Su structures showed a specific contact resistance of 4.0×10^<-2> and 1.5×10^<-5> Ω・cm, respectively. In Pt/BST/Pt/Ru/poly-Si capacitor structure formed at 500℃, leakage current characteristics and dielectric properties measured between top Pt and bottom Pt showed almost similar values to those measured between top Pt and poly-Si. The bottom electrode structures of Pt/Ru/poly-Si formed by MOCVD are greatly attractive for high density memory BST capacitor integration. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Ru buffer layer / Pt/dc sputtered Ru/poly-Si / Pt/MOCVD-Ru/Poly-Si / Contact |
| Paper # | ICD99-116 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 1999/7/23(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Bottom Electrode Structures of Pt/Ru Deposited on Polycrystalline Silicon for Semiconductor Memory Capacitors |
| Sub Title (in English) | |
| Keyword(1) | Ru buffer layer |
| Keyword(2) | Pt/dc sputtered Ru/poly-Si |
| Keyword(3) | Pt/MOCVD-Ru/Poly-Si |
| Keyword(4) | Contact |
| 1st Author's Name | Eun-Suck Choi |
| 1st Author's Affiliation | Department of Materials Engineering, Chungnam National University() |
| 2nd Author's Name | Jun-Sik Hwang |
| 2nd Author's Affiliation | Department of Materials Engineering, Chungnam National University |
| 3rd Author's Name | Jong-Bong Park |
| 3rd Author's Affiliation | Department of Materials Engineering, Chungnam National University / |
| 4th Author's Name | Soon-Gil Yoon |
| 4th Author's Affiliation | |
| Date | 1999/7/23 |
| Paper # | ICD99-116 |
| Volume (vol) | vol.99 |
| Number (no) | 234 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |