| Presentation | 1999/7/23 Production-Worthy Full Process Integration of Ta_2O_5 Capacitor Technology Chan Kim, Ki-Seon Park, Kyong-Min Kim, Min-Soo Kim, Sang-Kyoo Lee, Yo-Hwan Koh, Chung-Tae Kim, Nam-Jin Bae, Sang-Ho Kim, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A full process integration of Ta_2O_5/HSG capacitor technology has been developed for 1Gbit DRAM and beyond. This Ta_2O_5/HSG capacitor technology consists of the surface treatment of storage poly-Si, the cyclic Ta_2O_5 deposition, and the fully planarized PMD(pre-metal dielectrics) process. The excellent electrical properties of the Ta_2O_5 /HSG capacitor technology have been achieved in 1Gbit DRAM. The refresh time and the package level reliability tests in 0.32 μm DRAM demonstrated that the Ta_2O_5 capacitor technology in this work can be applied to DRAM mass products and is reliable. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Ta_2O_5 capacitor / PMD planarization / HSG / Surface treatment / cyclic Ta_2O_5 deposition / Refresh time / 0.32 μm DRAM products / Package level reliability |
| Paper # | ICD99-113 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 1999/7/23(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Production-Worthy Full Process Integration of Ta_2O_5 Capacitor Technology |
| Sub Title (in English) | |
| Keyword(1) | Ta_2O_5 capacitor |
| Keyword(2) | PMD planarization |
| Keyword(3) | HSG |
| Keyword(4) | Surface treatment |
| Keyword(5) | cyclic Ta_2O_5 deposition |
| Keyword(6) | Refresh time |
| Keyword(7) | 0.32 μm DRAM products |
| Keyword(8) | Package level reliability |
| 1st Author's Name | Chan Kim |
| 1st Author's Affiliation | Memory R & D Division, Hyundai Electronics Industries Co. Ltd.() |
| 2nd Author's Name | Ki-Seon Park |
| 2nd Author's Affiliation | Memory R & D Division, Hyundai Electronics Industries Co. Ltd. |
| 3rd Author's Name | Kyong-Min Kim |
| 3rd Author's Affiliation | Memory R & D Division, Hyundai Electronics Industries Co. Ltd. |
| 4th Author's Name | Min-Soo Kim |
| 4th Author's Affiliation | Memory R & D Division, Hyundai Electronics Industries Co. Ltd. |
| 5th Author's Name | Sang-Kyoo Lee |
| 5th Author's Affiliation | Memory R & D Division, Hyundai Electronics Industries Co. Ltd. |
| 6th Author's Name | Yo-Hwan Koh |
| 6th Author's Affiliation | Memory R & D Division, Hyundai Electronics Industries Co. Ltd. |
| 7th Author's Name | Chung-Tae Kim |
| 7th Author's Affiliation | Memory R & D Division, Hyundai Electronics Industries Co. Ltd. |
| 8th Author's Name | Nam-Jin Bae |
| 8th Author's Affiliation | APEX Co Ltd |
| 9th Author's Name | Sang-Ho Kim |
| 9th Author's Affiliation | APEX Co Ltd |
| Date | 1999/7/23 |
| Paper # | ICD99-113 |
| Volume (vol) | vol.99 |
| Number (no) | 234 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |