Presentation 1999/7/23
On-Chip Extraction of Interconnect Line Induced Delay Time for Quarter and Sub-Quarter Micron CMOS Technology
Hi-Deok Lee, Myoung-Jun Jang, Myoung-Kyu Park, Dae-Gwan Kang, Jeong-Mo Hwang,
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Abstract(in English) Interconnect parasitic parameters and their contribution to delay time are extracted on chip environment. Six kinds of test patterns are used to extract each interconnect parameters. The extracted parameters and their contribution to delay time are summarized in a look-up table. The circuit performance can be easily predicted using the look-up table. Moreover, the usefulness of the look-up table in designing repeaters is also shown.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Interconnect / Delay time / On-chip extraction / CMOS technology
Paper # ICD99-108
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Committee ICD
Conference Date 1999/7/23(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) On-Chip Extraction of Interconnect Line Induced Delay Time for Quarter and Sub-Quarter Micron CMOS Technology
Sub Title (in English)
Keyword(1) Interconnect
Keyword(2) Delay time
Keyword(3) On-chip extraction
Keyword(4) CMOS technology
1st Author's Name Hi-Deok Lee
1st Author's Affiliation R&D Division, LG Semicon Co., Ltd.()
2nd Author's Name Myoung-Jun Jang
2nd Author's Affiliation R&D Division, LG Semicon Co., Ltd.
3rd Author's Name Myoung-Kyu Park
3rd Author's Affiliation R&D Division, LG Semicon Co., Ltd.
4th Author's Name Dae-Gwan Kang
4th Author's Affiliation R&D Division, LG Semicon Co., Ltd.
5th Author's Name Jeong-Mo Hwang
5th Author's Affiliation R&D Division, LG Semicon Co., Ltd.
Date 1999/7/23
Paper # ICD99-108
Volume (vol) vol.99
Number (no) 234
Page pp.pp.-
#Pages 4
Date of Issue