講演名 | 1999/7/22 40nm Electron Beam Patterning by Optimization of Digitizing Method and Post Exposure Bake and its Application to Silicon Nano-Fabrication , |
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抄録(和) | |
抄録(英) | We experimented on the 40 nm paterning using E-beam lithography system. SAL601 negative E-beam resist was used for this experiment. In order to utilize the maximum ability of E-beam system, we reduced the PR thickness to 100 nm, and the field size to 200 μm. Then, PEB(Post Expose Bake) time and temperature, which is one of the very important factors for nano-patterning, were reduced for minimum line width. In addition, digitizing was optimized for better results. Quantum wire and quantum dot which can be used for nano-scale memory device, such as single electron memory device, were fabricated using these developed lithography technique. |
キーワード(和) | |
キーワード(英) | E-beam / SAL601 / Field size / PEB / digitizing method / nano-structure |
資料番号 | ICD99-76 |
発行日 |
研究会情報 | |
研究会 | ICD |
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開催期間 | 1999/7/22(から1日開催) |
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委員長氏名(和) | |
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幹事補佐氏名(和) | |
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講演論文情報詳細 | |
申込み研究会 | Integrated Circuits and Devices (ICD) |
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本文の言語 | ENG |
タイトル(和) | |
サブタイトル(和) | |
タイトル(英) | 40nm Electron Beam Patterning by Optimization of Digitizing Method and Post Exposure Bake and its Application to Silicon Nano-Fabrication |
サブタイトル(和) | |
キーワード(1)(和/英) | / E-beam |
第 1 著者 氏名(和/英) | / Sangyeon Han |
第 1 著者 所属(和/英) | Department of Electrical Engineering, KAIST |
発表年月日 | 1999/7/22 |
資料番号 | ICD99-76 |
巻番号(vol) | vol.99 |
号番号(no) | 233 |
ページ範囲 | pp.- |
ページ数 | 5 |
発行日 |