Presentation 1999/6/25
700MHz 288kb SRAM Macro with Expandable Architecture
H. Shimizu, K. Ijitsu, H. Akiyoshi, K. Aoyama, G. Itoh, H. Takatsuka, K. Watanabe, R. Nanjo, Y. Takao,
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Abstract(in English) Using 0.18μm CMOS technology, we have developed a 1.4ns access 700MHz 288kb embedded SRAM Macro. We attained this high speed characteristic by adopting pulsed decoder circuits and two stage sense amplifier (current sense for 1st stage and voltage sense for 2nd stage) circuit. This RAM macro can be expanded without speed loss.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) 0.18μm CMOS / SRAM / 700MHz / CACHE
Paper # ICD99-54
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Conference Date 1999/6/25(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) 700MHz 288kb SRAM Macro with Expandable Architecture
Sub Title (in English)
Keyword(1) 0.18μm CMOS
Keyword(2) SRAM
Keyword(3) 700MHz
Keyword(4) CACHE
1st Author's Name H. Shimizu
1st Author's Affiliation Advanced CMOS Technology Dept., Fujitsu Ltd.()
2nd Author's Name K. Ijitsu
2nd Author's Affiliation Advanced CMOS Technology Dept., Fujitsu Ltd.
3rd Author's Name H. Akiyoshi
3rd Author's Affiliation Advanced CMOS Technology Dept., Fujitsu Ltd.
4th Author's Name K. Aoyama
4th Author's Affiliation Advanced CMOS Technology Dept., Fujitsu Ltd.
5th Author's Name G. Itoh
5th Author's Affiliation Processor Development Dept., Fujitsu Ltd.
6th Author's Name H. Takatsuka
6th Author's Affiliation Technology Development Div. Fujitsu Ltd.
7th Author's Name K. Watanabe
7th Author's Affiliation Technology Development Div. Fujitsu Ltd.
8th Author's Name R. Nanjo
8th Author's Affiliation Technology Development Div. Fujitsu Ltd.
9th Author's Name Y. Takao
9th Author's Affiliation Technology Development Div. Fujitsu Ltd.
Date 1999/6/25
Paper # ICD99-54
Volume (vol) vol.99
Number (no) 150
Page pp.pp.-
#Pages 5
Date of Issue