Presentation 1999/4/16
High Level Logic Synthesis based on ALAP method
Yuji NOZASA, Kiyoshi FURUYA,
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Abstract(in English) In this paper, one method of the scheduling which determines execution time of eachoperation in High Level Logic Synthesis is described. The ALAP scheduling result is given at the initial stage, and it is searched to the one by one early step from the slowest step. This time, the heuristics which chooses the operation from the value which such operation determined transactions and multiple clock operation is used in the step which has not satisfied the resources constraint. By this heuristics, it is high-speed, and the sub-optimal location in which moreover, the quality is high has been obtained.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) High Level Logic Synthesis / ALAP scheduling / transaction / multiple / clock operation
Paper # ICD99-17
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Committee ICD
Conference Date 1999/4/16(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) High Level Logic Synthesis based on ALAP method
Sub Title (in English)
Keyword(1) High Level Logic Synthesis
Keyword(2) ALAP scheduling
Keyword(3) transaction
Keyword(4) multiple
Keyword(5) clock operation
1st Author's Name Yuji NOZASA
1st Author's Affiliation Department of Information and System Engineering, Faculty of Science and Engineering, Chuo University()
2nd Author's Name Kiyoshi FURUYA
2nd Author's Affiliation Department of Information and System Engineering, Faculty of Science and Engineering, Chuo University
Date 1999/4/16
Paper # ICD99-17
Volume (vol) vol.99
Number (no) 4
Page pp.pp.-
#Pages 6
Date of Issue