| Presentation | 1999/4/16 Fault Tolerant Design and Performance Analysis of Baseline Network with Duplicate Switches Takashi KODERA, Naotake KAMIURA, Yutaka HATA, Nobuyuki MATSUI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, we discuss the fault tolerant design and performance analysis of baseline network proposed as one of MINs (Multistage Interconnection Networks). For the network with n stages, we duplicate switches located at the first stage and n-th stage, and employ four-input two-output switches and two-input four-output ones to the second and (n-1)-th stages respectively. Then four paths are activated in the network and hence its fault tolerance and performance are enhanced. The comparison between our network and previously known ELMIN shows that the former is always superior in throughput to the latter and the former requires at most 1.34 times larger overheads with respect to hardware than the latter. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | MIN / baseline network / fault tolerance / duplicate / path |
| Paper # | ICD99-16 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 1999/4/16(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Fault Tolerant Design and Performance Analysis of Baseline Network with Duplicate Switches |
| Sub Title (in English) | |
| Keyword(1) | MIN |
| Keyword(2) | baseline network |
| Keyword(3) | fault tolerance |
| Keyword(4) | duplicate |
| Keyword(5) | path |
| 1st Author's Name | Takashi KODERA |
| 1st Author's Affiliation | Department of Computer Engineering, Himeji Institute of Technology() |
| 2nd Author's Name | Naotake KAMIURA |
| 2nd Author's Affiliation | Department of Computer Engineering, Himeji Institute of Technology |
| 3rd Author's Name | Yutaka HATA |
| 3rd Author's Affiliation | Department of Computer Engineering, Himeji Institute of Technology |
| 4th Author's Name | Nobuyuki MATSUI |
| 4th Author's Affiliation | Department of Computer Engineering, Himeji Institute of Technology |
| Date | 1999/4/16 |
| Paper # | ICD99-16 |
| Volume (vol) | vol.99 |
| Number (no) | 4 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |