Presentation 1999/4/16
An Approach to Locate Single Logical Faults in Sequential Circuits using Fault Simulation
Yutaka Murata, Koei Yamada, Koji Yamazaki, Teruhiko Yamada,
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Abstract(in English) We have proposed a technique for locating single faults in sequential circuits using erroneous paths tracing. However, this technique is a little difficult to achieve high diagnostic resolution. In this paper, we propose a fault location approach using fault simulation instead of erroneous paths tracing. Preliminary experimental results show that the diagnostic resolution can be improved about 40%.
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Keyword(in English) fault diagnosis / sequential circuits / logical faults / fault simulation
Paper # ICD99-15
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Conference Date 1999/4/16(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) An Approach to Locate Single Logical Faults in Sequential Circuits using Fault Simulation
Sub Title (in English)
Keyword(1) fault diagnosis
Keyword(2) sequential circuits
Keyword(3) logical faults
Keyword(4) fault simulation
1st Author's Name Yutaka Murata
1st Author's Affiliation Department of Computer Science, Meiji University()
2nd Author's Name Koei Yamada
2nd Author's Affiliation Department of Computer Science, Meiji University
3rd Author's Name Koji Yamazaki
3rd Author's Affiliation Department of Computer Science, Meiji University
4th Author's Name Teruhiko Yamada
4th Author's Affiliation Department of Computer Science, Meiji University
Date 1999/4/16
Paper # ICD99-15
Volume (vol) vol.99
Number (no) 4
Page pp.pp.-
#Pages 6
Date of Issue