Presentation 1999/4/16
Reduction of IDDQ Testing Time for Sequential Circuits
Yoshinobu Higami, Kewal K. Saluja, Yuzo Takamatsu, Kozo Kinoshita,
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Abstract(in English) With increasing testing time, the cost of testing increases. Therefore reduction of testing time is important. In IDDQ testing, since IDDQ measurement is a time-consuming process, reduction of test vectors for which IDDQ must be measured is more efficient for reducing the total testing time than reduction of the total number of test vectors. In this paper, we propose a method to select the small number of test vectors for which IDDQ must be measured, among a given test sequence. In the proposed method, we perform logic simulation in which the effect of faults is considered. Experimental results for ISCAS'89 benchmark circuits are presented to show the effectiveness of the proposed method.
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Keyword(in English) sequential circuit / IDDQ testing / testing time reduction / bridging fault / IDDQ measurement vectors
Paper # ICD99-14
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Conference Date 1999/4/16(1days)
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Paper Information
Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Reduction of IDDQ Testing Time for Sequential Circuits
Sub Title (in English)
Keyword(1) sequential circuit
Keyword(2) IDDQ testing
Keyword(3) testing time reduction
Keyword(4) bridging fault
Keyword(5) IDDQ measurement vectors
1st Author's Name Yoshinobu Higami
1st Author's Affiliation Ehime University()
2nd Author's Name Kewal K. Saluja
2nd Author's Affiliation University of Wisconsin
3rd Author's Name Yuzo Takamatsu
3rd Author's Affiliation Ehime University
4th Author's Name Kozo Kinoshita
4th Author's Affiliation Osaka University
Date 1999/4/16
Paper # ICD99-14
Volume (vol) vol.99
Number (no) 4
Page pp.pp.-
#Pages 8
Date of Issue