Presentation 1999/4/16
A Method of Test Generation for Iterative Logic Arrays
Kwame Osei Boateng, Hiroshi Takahashi, Yuzo Takamatsu,
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Abstract(in English) Circuit regularity is exploited in generating tests for iterative logic arrays (ILAs). A set of a constant number of test vectors that cover all the fault (of a given fault model) in any size of a given ILA is called a C-test for the ILA. In this paper, we first show that generating C-tests for ILAs is possible because input patterns applied (by each test vector) to the rows and columns of an array under test are repetitions of a few cell-input patterns. Next, we exploit this repetitive nature of the input patterns to develop a method of C-test generation for ILAs. Finally, we apply the proposed method to generate a C-test for the restoring array divider.
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Keyword(in English) test generation / iterative logic array / cell fault model / C-testable array / repetitive input pattern / C-test
Paper # ICD99-13
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Conference Date 1999/4/16(1days)
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Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Method of Test Generation for Iterative Logic Arrays
Sub Title (in English)
Keyword(1) test generation
Keyword(2) iterative logic array
Keyword(3) cell fault model
Keyword(4) C-testable array
Keyword(5) repetitive input pattern
Keyword(6) C-test
1st Author's Name Kwame Osei Boateng
1st Author's Affiliation Department of Computer Science Faculty of Engineering, Ehime University()
2nd Author's Name Hiroshi Takahashi
2nd Author's Affiliation Department of Computer Science Faculty of Engineering, Ehime University
3rd Author's Name Yuzo Takamatsu
3rd Author's Affiliation Department of Computer Science Faculty of Engineering, Ehime University
Date 1999/4/16
Paper # ICD99-13
Volume (vol) vol.99
Number (no) 4
Page pp.pp.-
#Pages 8
Date of Issue