Presentation 1999/4/16
Design of an Automatic Testing for FPGAs
Abderrahim Doumar, Toshiaki Ohmameuda, Hideo Ito,
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Abstract(in English) This paper presents a new design for testing SRAM-based field programmable gate arrays (FPGAs). The original SRAM part is modified a bit so that the FPGA gets the ability to automatically test itself. This method does not need a large outside FPGA memory (off-chip memory) and it can be used either by the company after fabrication of FPGA or by the normal users. It is proved that this method detects multiple faults, covers 100% of modeled faults and the test time is very short comparing with other approaches. The simulation results of Xilinix XC4000 family, using CAD tools, shows that the routing and the placement of this method are easily achieved.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Field programmable gate array (FPGA) / testing / Design for testing / Shifting configurations / Programmability
Paper # ICD99-12
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Conference Date 1999/4/16(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Design of an Automatic Testing for FPGAs
Sub Title (in English)
Keyword(1) Field programmable gate array (FPGA)
Keyword(2) testing
Keyword(3) Design for testing
Keyword(4) Shifting configurations
Keyword(5) Programmability
1st Author's Name Abderrahim Doumar
1st Author's Affiliation Graduate School of Science and Technology, Chiba University, Japan()
2nd Author's Name Toshiaki Ohmameuda
2nd Author's Affiliation Department of Information and Image Sciences, Chiba University, Japan
3rd Author's Name Hideo Ito
3rd Author's Affiliation Department of Information and Image Sciences, Chiba University, Japan
Date 1999/4/16
Paper # ICD99-12
Volume (vol) vol.99
Number (no) 4
Page pp.pp.-
#Pages 8
Date of Issue