| Presentation | 1999/4/16 Saving memory for verification of asynchronous circuits Kouhei Oikawa, Kouta Kitamura, Tomohiro Yoneda, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The typical problems which arise in the formal verification of practical circuits are that the verification often needs long CPU times and huge amount of memory. In particular, for the verifiers of real-time systems the limitation on memory sizes tends to be the bottleneck, because those verifiers usually use the explicit state representations. In this work, we focus on reducing the memory use in the verification method of bounded asynchronous circuits, and propose techniques for sharing, compressing, and thinning out the visited state information. The experimental results with STARI circuits show that combining those techniques is effective, and reduces the memory use to 1/5. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | state space explosion / formal verification / time petri net / trace theory / asynchronous circuit |
| Paper # | ICD99-11 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 1999/4/16(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Saving memory for verification of asynchronous circuits |
| Sub Title (in English) | |
| Keyword(1) | state space explosion |
| Keyword(2) | formal verification |
| Keyword(3) | time petri net |
| Keyword(4) | trace theory |
| Keyword(5) | asynchronous circuit |
| 1st Author's Name | Kouhei Oikawa |
| 1st Author's Affiliation | Graduate School of Information Science and Engineering, Department of Computer Science Tokyo Institute of Technology() |
| 2nd Author's Name | Kouta Kitamura |
| 2nd Author's Affiliation | Graduate School of Information Science and Engineering, Department of Computer Science Tokyo Institute of Technology |
| 3rd Author's Name | Tomohiro Yoneda |
| 3rd Author's Affiliation | Graduate School of Information Science and Engineering, Department of Computer Science Tokyo Institute of Technology |
| Date | 1999/4/16 |
| Paper # | ICD99-11 |
| Volume (vol) | vol.99 |
| Number (no) | 4 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |