Presentation 1999/4/16
Digital Vision Chip Based on S^3PE Architecture and Its High Integration
Kazuya Ogawa, Takashi Komuro, Idaku Ishii, Masatoshi Ishikawa,
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Abstract(in English) In this paper we describe a general-purpose digital vision chip based on the S^3PE archi tecture in which a digital genaral-purpose processor and a photo detector are integrated in a single pixel. To realize a highly integrated vision chip, we developed a test chip in which 16×16 pixels are integrated by using 0.35μm CMOS technology. The area of each pixel is 150×150μm, allowing the possibility of integrating 64×64 pixels in a single chip. The architecture, design and experimental results of the chip will be described.
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Keyword(in English) vision chip / massively parallel processing / image processing / VLSI
Paper # ICD99-7
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Conference Date 1999/4/16(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
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Title (in English) Digital Vision Chip Based on S^3PE Architecture and Its High Integration
Sub Title (in English)
Keyword(1) vision chip
Keyword(2) massively parallel processing
Keyword(3) image processing
Keyword(4) VLSI
1st Author's Name Kazuya Ogawa
1st Author's Affiliation Department of Mathematical Engineering and Information Physics, Graduate School of Engineering, University of Tokyo()
2nd Author's Name Takashi Komuro
2nd Author's Affiliation Department of Mathematical Engineering and Information Physics, Graduate School of Engineering, University of Tokyo
3rd Author's Name Idaku Ishii
3rd Author's Affiliation Department of Mathematical Engineering and Information Physics, Graduate School of Engineering, University of Tokyo
4th Author's Name Masatoshi Ishikawa
4th Author's Affiliation Department of Mathematical Engineering and Information Physics, Graduate School of Engineering, University of Tokyo
Date 1999/4/16
Paper # ICD99-7
Volume (vol) vol.99
Number (no) 4
Page pp.pp.-
#Pages 7
Date of Issue