| Presentation | 1994/11/24 Multi-Chip Module and Known Good Die Process Yutaka Tsukada, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The quality and productivity of MCM highly depend on the quality level of semiconductors attached to its substrate.No matter the technology of MCM is,this is a common problem to all.Since the eleament of technologies to achieve high performance as well as low cost MCM's are available,KGD is the last and major unresolved infrastructure.KGD process contains the treatment to assure the physical quality level as well as the electrical one.This paper describes the contents of KGD and the present status with including the relation to the test.Single chip deck burn-in is introduced as one of the typical KGD process which is in producticn pracice today. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Bare chip attach / Self test / Burn-in / Boundary Scan |
| Paper # | ICD94-143 |
| Date of Issue |
| Conference Information | |
| Committee | ICD |
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| Conference Date | 1994/11/24(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Multi-Chip Module and Known Good Die Process |
| Sub Title (in English) | |
| Keyword(1) | Bare chip attach |
| Keyword(2) | Self test |
| Keyword(3) | Burn-in |
| Keyword(4) | Boundary Scan |
| 1st Author's Name | Yutaka Tsukada |
| 1st Author's Affiliation | Yasu laboratory,IBM Japan() |
| Date | 1994/11/24 |
| Paper # | ICD94-143 |
| Volume (vol) | vol.94 |
| Number (no) | 360 |
| Page | pp.pp.- |
| #Pages | 7 |
| Date of Issue | |