Presentation 1994/11/24
16M bit Synchronous DRAM with 64 bit data compressed Test Mode
Seiji Sawada, Hisashi Iwamoto, Takashi Araki, Yasumitsu Murai, Yasuhiro Konishi, Masaki Kumanoya,
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Abstract(in English) Although synchronous DRAMs can transfer the burst data at 100MHz, conventional 30-60MHz testers will be used in mass production to check as many items as possible to keep manufacturing cost including tester cost as low as possible.On the other hand,this will bring longer testing time due to low burst data rate.A newly developed test mode overcomes this dilemma because the test mode compresses 64bits burst data into 1bit.At 30MHz,total testing time is reduced to 45% in write cycle and 75% in read cycle.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) SDRAM / synchronous DRAM / high speed DRAM / test mode
Paper # ICD94-140
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Conference Date 1994/11/24(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) 16M bit Synchronous DRAM with 64 bit data compressed Test Mode
Sub Title (in English)
Keyword(1) SDRAM
Keyword(2) synchronous DRAM
Keyword(3) high speed DRAM
Keyword(4) test mode
1st Author's Name Seiji Sawada
1st Author's Affiliation Kitaitami Works,Mitsubishi Electric Corp.()
2nd Author's Name Hisashi Iwamoto
2nd Author's Affiliation ULSI Laboratory,Mitsubishi Electric Corp.
3rd Author's Name Takashi Araki
3rd Author's Affiliation ULSI Laboratory,Mitsubishi Electric Corp.
4th Author's Name Yasumitsu Murai
4th Author's Affiliation Mitsubishi Electric Engineering Company Ltd.
5th Author's Name Yasuhiro Konishi
5th Author's Affiliation Kitaitami Works,Mitsubishi Electric Corp.
6th Author's Name Masaki Kumanoya
6th Author's Affiliation Kitaitami Works,Mitsubishi Electric Corp.
Date 1994/11/24
Paper # ICD94-140
Volume (vol) vol.94
Number (no) 360
Page pp.pp.-
#Pages 7
Date of Issue