| Presentation | 1994/6/24 A Monolithic 156Mb/s Clock and Data-Recovery PLL Circuit using the Sample-and-Hold Technique Noboru Ishihara, Yukio Akazawa, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper describes a fully monolithic,adjustment-free clock and data recovery PLL circuit that has no external components except a by-pass capacitor.A test chip fabricated using a Si bipolar process exhibits error free operation for a data date of 156 Mb, s and pseudo random bit sequence(PRBS)data of 2^23>-1 with rms data pattern jitter of 1.2 degrees. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Clock Recovery / Decision Circuit / Phase Locked Loop / Sample and Hold Circuit / Si-bipolar |
| Paper # | ICD94-68 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 1994/6/24(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Monolithic 156Mb/s Clock and Data-Recovery PLL Circuit using the Sample-and-Hold Technique |
| Sub Title (in English) | |
| Keyword(1) | Clock Recovery |
| Keyword(2) | Decision Circuit |
| Keyword(3) | Phase Locked Loop |
| Keyword(4) | Sample and Hold Circuit |
| Keyword(5) | Si-bipolar |
| 1st Author's Name | Noboru Ishihara |
| 1st Author's Affiliation | NTT() |
| 2nd Author's Name | Yukio Akazawa |
| 2nd Author's Affiliation | NTT |
| Date | 1994/6/24 |
| Paper # | ICD94-68 |
| Volume (vol) | vol.94 |
| Number (no) | 125 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |