Presentation 1994/6/24
Low Power 11x320 Mbps Prallel Transmitter/Receiver LSIs for 2. 4Gbps Optical Link
Takahiro Kamei, Nobuyuki Miyahara, Takashi Taya, Shinsuke Yamaoka,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) We have developed a monolithic transmitter LSI with 12 LD drivers and a receiver LSI with 12 post amplifiers for a multi- channel parallel optical link, using a scrambling code and a new silicon-bipolar processing technology suitable for low-power applications.The transmitter and receiver modules,which contain these LSIs for 2.4Gbps up to 100m for ATM transmission system, occupy 14x4lxl4Omm^3 respectively and consume a total of 5.2W.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) parallel optical link / B-ISDN / ATM switch / Si-bipolar / scrambleng code
Paper # ICD94-63
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Conference Date 1994/6/24(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Low Power 11x320 Mbps Prallel Transmitter/Receiver LSIs for 2. 4Gbps Optical Link
Sub Title (in English)
Keyword(1) parallel optical link
Keyword(2) B-ISDN
Keyword(3) ATM switch
Keyword(4) Si-bipolar
Keyword(5) scrambleng code
1st Author's Name Takahiro Kamei
1st Author's Affiliation VLSI Research & Development Center,Oki Electric Industry Co.,Ltd.()
2nd Author's Name Nobuyuki Miyahara
2nd Author's Affiliation VLSI Research & Development Center,Oki Electric Industry Co.,Ltd.
3rd Author's Name Takashi Taya
3rd Author's Affiliation Integrated Design Center,OkiElectric Industry Co.,Ltd.
4th Author's Name Shinsuke Yamaoka
4th Author's Affiliation Integrated Design Center,OkiElectric Industry Co.,Ltd.
Date 1994/6/24
Paper # ICD94-63
Volume (vol) vol.94
Number (no) 125
Page pp.pp.-
#Pages 7
Date of Issue