Presentation 1994/6/24
3.0Gb/s,272mW,8:1Multiplexer and 4.1Gb/s,388mW,1:8 Demultiplexer
Kimio Ueda, Nagisa Sasaki, Hisayasu Sato, Shunji Kubo, koichiro Mashiko,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) This paper descrides the,8:1 multiplexer and the 1:8 demultiplexer chips with power dissipation.These chips adopt the new architectures which require smaller hardware.Also,circuit optimization was carried out. They were fabricated using 0.8μm dou ble polysilicon self-aligned technology with trench isolation.The multiplexer dissipates 272m W at a data rate of 3.0Gb, s,while the demultiplexer dissipates 388mW at a data rate of 4.1 Gb/s.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Sibipolar / Multiplexer / Demultiplexer
Paper # ICD94-60
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Conference Date 1994/6/24(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) 3.0Gb/s,272mW,8:1Multiplexer and 4.1Gb/s,388mW,1:8 Demultiplexer
Sub Title (in English)
Keyword(1) Sibipolar
Keyword(2) Multiplexer
Keyword(3) Demultiplexer
1st Author's Name Kimio Ueda
1st Author's Affiliation System LSI Laboratory,Mitsubishi Electric Corp.()
2nd Author's Name Nagisa Sasaki
2nd Author's Affiliation System LSI Laboratory,Mitsubishi Electric Corp.
3rd Author's Name Hisayasu Sato
3rd Author's Affiliation System LSI Laboratory,Mitsubishi Electric Corp.
4th Author's Name Shunji Kubo
4th Author's Affiliation ULSI Laboratory,Mitsubishi Electric Corp.
5th Author's Name koichiro Mashiko
5th Author's Affiliation System LSI Laboratory,Mitsubishi Electric Corp.
Date 1994/6/24
Paper # ICD94-60
Volume (vol) vol.94
Number (no) 125
Page pp.pp.-
#Pages 6
Date of Issue