| Presentation | 1994/9/22 High Speed Algorithm for Monte Carlo Device Simulation with Parallel Processors Yoshihisa Yoshida, Reiji Aibara, Tamio Shimatani, Norihiko Kuroishi, Tetsuro Kawada, Nobuaki Miyakawa, Mitsumasa Koyanagi, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Device simulation with Monte Carlo method,in which caxriers in a device axe treated as paxticles can deal with nonlinear physical phenomenon.Because Monte Carlo method is a statistical numerical method,if n times accuracy is required by reducing statistical errors,n^2 samples axe needed.In this paper,we propose an algorithm for Monte Carlo device simulation with highly parallel processors.The processor architecture we suppose is high speed,one way ring bus structure.We evaluated the algorithm by software simulation using multitask facilities.Major parts of Monte Carlo device simulation are divided into potential caliculation by solving poisson equations and determination of motion of paxticles. Each part of the algorithm is implemented in parallel.We demonstrate an estimation that total execution speed will efficiently increase up to 100 processors on the ring bus architecture. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Monte Carlo Method / Device Simulation / Parallel Processing / Ring Bus Architecture |
| Paper # | ICD94-114 |
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| Committee | ICD |
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| Conference Date | 1994/9/22(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | High Speed Algorithm for Monte Carlo Device Simulation with Parallel Processors |
| Sub Title (in English) | |
| Keyword(1) | Monte Carlo Method |
| Keyword(2) | Device Simulation |
| Keyword(3) | Parallel Processing |
| Keyword(4) | Ring Bus Architecture |
| 1st Author's Name | Yoshihisa Yoshida |
| 1st Author's Affiliation | Reseach Center for Integrated Systems,Hiroshima University() |
| 2nd Author's Name | Reiji Aibara |
| 2nd Author's Affiliation | Reseach Center for Integrated Systems,Hiroshima University |
| 3rd Author's Name | Tamio Shimatani |
| 3rd Author's Affiliation | Department of Machine Inteligence and System Engineering,Faculty of Engineering,Tohoku University |
| 4th Author's Name | Norihiko Kuroishi |
| 4th Author's Affiliation | Electronic Imaging & Devices Reseach Laboratory,Fuji Xerox Co.,Ltd |
| 5th Author's Name | Tetsuro Kawada |
| 5th Author's Affiliation | Electronic Imaging & Devices Reseach Laboratory,Fuji Xerox Co.,Ltd |
| 6th Author's Name | Nobuaki Miyakawa |
| 6th Author's Affiliation | Electronic Imaging & Devices Reseach Laboratory,Fuji Xerox Co.,Ltd |
| 7th Author's Name | Mitsumasa Koyanagi |
| 7th Author's Affiliation | Department of Machine Inteligence and System Engineering,Faculty of Engineering,Tohoku University |
| Date | 1994/9/22 |
| Paper # | ICD94-114 |
| Volume (vol) | vol.94 |
| Number (no) | 244 |
| Page | pp.pp.- |
| #Pages | 8 |
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