Presentation 1994/9/22
A Ultra Low Power Charge-Recyding Bus Architecture for Super High Data-Rate ULSI′s
Hiroyuki Yamauchi, Hironori Akamatsu, Tsutomu Fujita,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) A Charge-Recycling Bus(CRB)architecture,featuring virtual stacking of the individual bus-capacitance into a sedes configuration between supply voltage and ground,has been proposed. This CRB architecture makes it possible to reduce not only each bus-swing but also a total equivalent bus capacitance of the ultra multi-bit buses running in parallel.The voltage swing of each bus is given by the recycled charge supplying from the upper adjacent bus capacitance,instead of the power line.The dramatical power reduction to 1, m2 of conventional full swing bus scheme one was verified by the simulated and measured data.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Charge-Recycling / Suppressed bus swing / Super high data-rate
Paper # ICD94-112
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Committee ICD
Conference Date 1994/9/22(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Ultra Low Power Charge-Recyding Bus Architecture for Super High Data-Rate ULSI′s
Sub Title (in English)
Keyword(1) Charge-Recycling
Keyword(2) Suppressed bus swing
Keyword(3) Super high data-rate
1st Author's Name Hiroyuki Yamauchi
1st Author's Affiliation MATSUSHITA ELECTRIC Industrial Co.,Ltd.()
2nd Author's Name Hironori Akamatsu
2nd Author's Affiliation MATSUSHITA ELECTRIC Industrial Co,Ltd.
3rd Author's Name Tsutomu Fujita
3rd Author's Affiliation MATSUSHITA ELECTRIC Industrial Co,Ltd.
Date 1994/9/22
Paper # ICD94-112
Volume (vol) vol.94
Number (no) 244
Page pp.pp.-
#Pages 8
Date of Issue