Presentation 1994/8/25
3-D CG Media Chip:An Experimental Single-chip Architecture for Three-Dimensional Computer Graphics
Takao Watanabe, Kazusige Ayukawa, Yoshinobu Nakagome,
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Abstract(in English) A single-chip architecture for three-dimensional(3-D)computer graphics(CG)is discussed assuming portable equipment with a 3-D CG interface.An on-chip DRAM cell array for two 3-D frame buffers and one 2-D frame buffer,the on-chip pixel generator,the on-chip frame synthesizer,parallel alpha-blending and Z-comparison circuits attached to the DRAM cell array are proposed.Estimation of the chip performance,assuming the 0.35-μm CMOS design rule and a volta ge of 3.3 V,shows that the chip size,power dissipation,the drawing speed,and the memory data I, O rate would be 14 x 13.5 mm,590 mw,0. 25 milhon polygons/s,and 1 gigabyte/s,respectively.Based on circuit simulations,the chip can run on a 1.5-V dry cell.A scaled- down version of the chip is being fabricated for evaluation.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) DRAM / Computer Graphics
Paper # ICD94-84
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Conference Date 1994/8/25(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) 3-D CG Media Chip:An Experimental Single-chip Architecture for Three-Dimensional Computer Graphics
Sub Title (in English)
Keyword(1) DRAM
Keyword(2) Computer Graphics
1st Author's Name Takao Watanabe
1st Author's Affiliation Central Research Laboratory,Hitachi,Ltd.()
2nd Author's Name Kazusige Ayukawa
2nd Author's Affiliation Central Research Laboratory,Hitachi,Ltd.
3rd Author's Name Yoshinobu Nakagome
3rd Author's Affiliation Central Research Laboratory,Hitachi,Ltd.
Date 1994/8/25
Paper # ICD94-84
Volume (vol) vol.94
Number (no) 203
Page pp.pp.-
#Pages 7
Date of Issue