Presentation 1999/1/20
Thermal Capacitance Noise and Operation Reliability of High-Speed Ultimate-Low Power MOS Circuit
Masaaki Hayashi, Chugo Fujihashi,
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Abstract(in English) Low power technology for a high speed circuit may be ultimately required to be reached to a level where the circuit is operated with countable small number electrons. For analysis of thermal energy noise, a probability for the number of electrons in a load capacitance induced by thermal energy is derived. The probability is combined with a probability for the number of electrons in the load capacitance by external voltage, and then a combined probability for total noise effect is derived. Operation reliability is examined by error probability based on the combined probability/
Keyword(in Japanese) (See Japanese page)
Keyword(in English) MOS / Super-high-speed / Low power / Operation reliability / thermal capacity noise / Dynamic inverter
Paper # ED98-196,MW98-159,ICD98-263
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Conference Date 1999/1/20(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Thermal Capacitance Noise and Operation Reliability of High-Speed Ultimate-Low Power MOS Circuit
Sub Title (in English)
Keyword(1) MOS
Keyword(2) Super-high-speed
Keyword(3) Low power
Keyword(4) Operation reliability
Keyword(5) thermal capacity noise
Keyword(6) Dynamic inverter
1st Author's Name Masaaki Hayashi
1st Author's Affiliation Department of Eldctronic Engineering, Tokyo Institute of Polytechnics()
2nd Author's Name Chugo Fujihashi
2nd Author's Affiliation Department of Eldctronic Engineering, Tokyo Institute of Polytechnics
Date 1999/1/20
Paper # ED98-196,MW98-159,ICD98-263
Volume (vol) vol.98
Number (no) 523
Page pp.pp.-
#Pages 7
Date of Issue