| Presentation | 1998/7/23 A Non-Feedback Skew Suppression Circuit, Synchronous Mirror Delay Takanori Saeki, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper describes a Synchronous Mirror Delay(SMD)that is able to suppress the clock skew and generate a duty 50% clock and a double frequency clock in only two clock cycles.It describes that the basic circuit stucture and operation of the SMD.The SMD design incorporates a counter control scheme for size reduction, an interleaved scheme for digital jitter suppression and a direct skew-detection scheme that is applicable to unfixed clock path devices such as ASICs. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Synchronous Mirror Delay / Clock Skew / Non-Feedback / PLL / Jitter |
| Paper # | SDM98-87,ICD98-86 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 1998/7/23(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Vice Chair | |
| Secretary | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Non-Feedback Skew Suppression Circuit, Synchronous Mirror Delay |
| Sub Title (in English) | |
| Keyword(1) | Synchronous Mirror Delay |
| Keyword(2) | Clock Skew |
| Keyword(3) | Non-Feedback |
| Keyword(4) | PLL |
| Keyword(5) | Jitter |
| 1st Author's Name | Takanori Saeki |
| 1st Author's Affiliation | ULSI Device Development Laboratories, NEC Corporation() |
| Date | 1998/7/23 |
| Paper # | SDM98-87,ICD98-86 |
| Volume (vol) | vol.98 |
| Number (no) | 195 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |