Presentation 1998/7/23
A CMOS Scheme for 0.5V Supply Voltage with Pico-Ampere Standby Current
Hiroshi Kawaguchi, Kouichi Nose, Takayasu Sakurai,
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Abstract(in English) If a VLSI should be operated in 0.5V~0.8V VDD range for low-power consumption, the threshold voltage of MOSFET's VTH, should be well below 0.5V to turn the MOSFET's on.The low VTH like 0.1V~0.2V, however, causes 10nA order subthreshold leakage current per logic gate in a standby mode, which leads to 10mA order standby current for one million gate VLSI's.In this paper, super cut-off CMOS(SCCMOS) circuit is proposed to overcome this situation.With the SCCMOS, an operation is possible under 0.5V~0.8V VDD with 0.1V~0.2V VTH and at the same time pA order standby current per logic gate can be achieved.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Low power / Standby current / SCCMOS / Pass-transistor
Paper # SDM98-83,ICD98-82
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Conference Date 1998/7/23(1days)
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Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A CMOS Scheme for 0.5V Supply Voltage with Pico-Ampere Standby Current
Sub Title (in English)
Keyword(1) Low power
Keyword(2) Standby current
Keyword(3) SCCMOS
Keyword(4) Pass-transistor
1st Author's Name Hiroshi Kawaguchi
1st Author's Affiliation Institute of Industrial Science, University of Tokyo()
2nd Author's Name Kouichi Nose
2nd Author's Affiliation Institute of Industrial Science, University of Tokyo
3rd Author's Name Takayasu Sakurai
3rd Author's Affiliation Institute of Industrial Science, University of Tokyo
Date 1998/7/23
Paper # SDM98-83,ICD98-82
Volume (vol) vol.98
Number (no) 195
Page pp.pp.-
#Pages 5
Date of Issue