Presentation	1998/10/16 A Pipeline-Operating, Fast Row-Cycle Memory FCRAM in High-Speed DRAM Architecture Movement Masao Taguchi,
PDF Download Page	PDF download Page Link
Abstract(in Japanese)	(See Japanese page)
Abstract(in English)	We propose a memory FCRAM built on a new operating scheme by way of reviewing architectural improvements in DRAMs. A pipelining scheme, including row-address circuitry, combined with auto-precharge control allowed to achieve a short cycle time of 20ns for the same bank access. This device is suitable for multi-media or the like applications because of the fast random cycle and the simple command set like an SRAM. Using a multi-chip assembly technique, the performance is expected to be equivalent to an embedded memory structure. The performance showed that this scheme might be evolved to an IP-core for system LSIs or system memories.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	DRAM / FCRAM / Cycle time / Core architecture
Paper #	DSP98-108,ICD98-195,CPSY98-110
Date of Issue

Conference Information
Committee	ICD
Conference Date	1998/10/16(1days)
Place (in Japanese)	(See Japanese page)
Place (in English)
Topics (in Japanese)	(See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To	Integrated Circuits and Devices (ICD)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	A Pipeline-Operating, Fast Row-Cycle Memory FCRAM in High-Speed DRAM Architecture Movement
Sub Title (in English)
Keyword(1)	DRAM
Keyword(2)	FCRAM
Keyword(3)	Cycle time
Keyword(4)	Core architecture
1st Author's Name	Masao Taguchi
1st Author's Affiliation	DRAM Division, Fujitsu Limited()
Date	1998/10/16
Paper #	DSP98-108,ICD98-195,CPSY98-110
Volume (vol)	vol.98
Number (no)	321
Page	pp.pp.-
#Pages	8
Date of Issue