| Presentation | 1998/10/16 High-speed SRAM Macros using a Configurable Organization Technique with an Automatic Timing Adjuster Kazumasa Ando, Keiichi Higeta, Yasuhiro Fujimura, Kazutaka Mori, Michiaki Nakayama, Hiroaki Nambu, Kazuhisa Miyamoto, Kunihiko Yamaguchi, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The key to improving the performance of the cache system of a single chip processor is to incorporate appropriate varieties of SRAM macros. The configurable organization technique and the automatic timing adjuster help word/bit-flexible configuration of functional units while preserving each organization's performance. In addition, a low Vth MOS transistor is applied to improve access time. To overcome the increase in current leakage due to a low Vth, a back-bias control circuit is also proposed. These techniques in conjunction with a 0.25-um CMOS process make it possible to achieve a 0.9-ns-access, 700-MHz SRAM macros. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | CMOS / SRAM / Configurable Organization / Sense Amplifier / Back-bias |
| Paper # | DSP98-107,ICD98-194,CPSY98-109 |
| Date of Issue |
| Conference Information | |
| Committee | ICD |
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| Conference Date | 1998/10/16(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | High-speed SRAM Macros using a Configurable Organization Technique with an Automatic Timing Adjuster |
| Sub Title (in English) | |
| Keyword(1) | CMOS |
| Keyword(2) | SRAM |
| Keyword(3) | Configurable Organization |
| Keyword(4) | Sense Amplifier |
| Keyword(5) | Back-bias |
| 1st Author's Name | Kazumasa Ando |
| 1st Author's Affiliation | Device Development Center, Hitachi Ltd.() |
| 2nd Author's Name | Keiichi Higeta |
| 2nd Author's Affiliation | Device Development Center, Hitachi Ltd. |
| 3rd Author's Name | Yasuhiro Fujimura |
| 3rd Author's Affiliation | Device Development Center, Hitachi Ltd. |
| 4th Author's Name | Kazutaka Mori |
| 4th Author's Affiliation | Device Development Center, Hitachi Ltd. |
| 5th Author's Name | Michiaki Nakayama |
| 5th Author's Affiliation | Device Development Center, Hitachi Ltd. |
| 6th Author's Name | Hiroaki Nambu |
| 6th Author's Affiliation | Central Research Laboratory, Hitachi Ltd. |
| 7th Author's Name | Kazuhisa Miyamoto |
| 7th Author's Affiliation | General Purpose Computer Division, Hitachi Ltd. |
| 8th Author's Name | Kunihiko Yamaguchi |
| 8th Author's Affiliation | Hitachi ULSI Systems, Corp. |
| Date | 1998/10/16 |
| Paper # | DSP98-107,ICD98-194,CPSY98-109 |
| Volume (vol) | vol.98 |
| Number (no) | 321 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |