| Presentation | 1998/10/15 Prescaler PLL Frequency Synthesizer with Multi-Programmable Dividers Yasuaki SUMI, Ryosuke FURUHASHI, Hidekazu ISHII, Shigeki OBOTE, Naoki KITAI, Yutaka FUKUI, |
|---|---|
| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Nowadays, in the fields of telecommunications and the multi media interfaces devices, the PLL(Phase Locked Loop)frequency synthesizer used as a local oscillation circuit is requested theshift to the high frequency region in order to correspond to an increase in the number of channels. In general, to reduce the load of the programmable divider at a high frequency operation, the prescaler method is used where a prescaler is installed in front of the programmable divider. However, there is a problem of the performance deterioration due to the decrease in a reference frequency by the prescaler method. In this paper we have proposed that the new prescaler PLL frequency synthesizer with multi-programmable. In order to treat a higher frequency, we use the prescaler method aggressively, we will be prevent the performance deterioration in prescaler method by intorducing the mult-programmable dividers into prescaler method. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | PLL frequency synthesizer / prescaler / multi programmable divider / programmable divider / and hig speed lockup |
| Paper # | DSP98-97,ICD98-184,CPSY98-99 |
| Date of Issue |
| Conference Information | |
| Committee | ICD |
|---|---|
| Conference Date | 1998/10/15(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Prescaler PLL Frequency Synthesizer with Multi-Programmable Dividers |
| Sub Title (in English) | |
| Keyword(1) | PLL frequency synthesizer |
| Keyword(2) | prescaler |
| Keyword(3) | multi programmable divider |
| Keyword(4) | programmable divider |
| Keyword(5) | and hig speed lockup |
| 1st Author's Name | Yasuaki SUMI |
| 1st Author's Affiliation | Tottori SANYO Electric Co., Ltd.() |
| 2nd Author's Name | Ryosuke FURUHASHI |
| 2nd Author's Affiliation | Department of Electrical and Electronic Engineering, Faculty of Engineering, Tottori University |
| 3rd Author's Name | Hidekazu ISHII |
| 3rd Author's Affiliation | Department of Electrical and Electronic Engineering, Faculty of Engineering, Tottori University |
| 4th Author's Name | Shigeki OBOTE |
| 4th Author's Affiliation | Department of Electrical and Electronic Engineering, Faculty of Engineering, Tottori University |
| 5th Author's Name | Naoki KITAI |
| 5th Author's Affiliation | Department of Electrical and Electronic Engineering, Faculty of Engineering, Tottori University |
| 6th Author's Name | Yutaka FUKUI |
| 6th Author's Affiliation | Department of Electrical and Electronic Engineering, Faculty of Engineering, Tottori University |
| Date | 1998/10/15 |
| Paper # | DSP98-97,ICD98-184,CPSY98-99 |
| Volume (vol) | vol.98 |
| Number (no) | 320 |
| Page | pp.pp.- |
| #Pages | 7 |
| Date of Issue | |